The present invention relates to the fabrication of integrated circuits (ICs) and more particularly to a system and method for automatically transforming a compacted layout of an IC to a relaxed layout which satisfies an overall dimensional constraint.
In the design of ICs, it is a goal to minimize the area occupied by the circuits which make up an integrated circuit. Minimized area usually equates to good circuit performance. Signal conductors are shorter when area is minimized, thus reducing parasitic capacitance and resistance of the signal conductors, which in turn, makes the circuits faster.
Accordingly, tools used in the automated design of ICs, known as electronic design automation (“EDA”) tools, tend to minimize the layout area occupied by circuits of an IC. Typically, in such automated design, a circuit design is generated by a circuit design engineer with the aid of EDA tools. From the circuit design, a set of layouts are generated for devices and/or wiring at each level of the IC.
In generating such layout, a compacting process is typically performed, in which the sizes of features and spacings between features, e.g. devices, conductive lines, etc. of the layout are reduced to minimum sizes and spacings while still preserving connections between such features. This results in the layout having minimized area.
Typically, each level of the IC is defined by a set of layouts containing the patterns for respective circuit blocks of the IC. Thus, for a particular level of an IC, a first layout is generated from a circuit design for a first circuit block, second layout is generated for a second circuit block, and so on. As part of generating a layout for a circuit block, the layout is compacted by reducing the spacings between features and sometimes the sizes of features themselves to minimum values while preserving the connections between the features of the layout. Generally, there is little flexibility to vary the sizes of features, particularly the width of conductive lines. Therefore, compacting is generally directed to reducing only the width of spacings between features.
The resulting layout must fit within the available area for the particular circuit block. In a conventional Manhattan layout, the layout spans an area of a substrate extending in a horizontal direction (the direction parallel to most lines of the layout), and also extends in a vertical direction (the direction transverse to the horizontal lines). The area available for the layout is defined by a dimensional constraint in the horizontal direction and another dimensional constraint in the vertical direction. Thus, the compacted layout must fit within the dimensional constraints provided for the circuit block in both the horizontal direction and the vertical direction.
In each of the horizontal and vertical directions, a layout can be considered to be a collection of parallel paths that are placed side-by-side. Each path of the layout runs from one edge of the layout to an opposite edge of the layout. For example, in a vertical direction, each path runs between a bottom edge and a top edge of the layout. Each path typically includes a set of modifiable elements such as segments of conductive lines, active areas, isolation trenches, etc., as well as spacings between such modifiable elements. Alternatively, each path can include only segments of conductive lines and the spacings between them, as in a layout for a metallization pattern. As used herein, the term “features” means any such modifiable elements. The processing of a layout on the basis of the spacings between features of the paths which make up the layout provides convenient granularity.
Unfortunately, the conventional process of compacting a layout to minimum sizes and spacings can unnecessarily complicate the manufacturing process and increase the likelihood of failure. Both the fabrication of photomasks and lithographic patterning of a semiconductor substrate are very sensitive to contamination and variations in the manufacturing process. Such sensitivity increases as the spacings between features of a layout are decreased. The more features of a mask or wafer pattern that are placed at minimum spacings, the more susceptible the mask or wafer pattern becomes subject to ruination during manufacture by particle contamination such as from dust. Also, variations in the manufacturing process, for example, lithographic process variations and etching variations, affect masks and wafer patterns to a greater extent when the spacings between features are small.
Moreover, it often occurs that the spacings between certain features of a layout need not be reduced to minimum values. In an example, some paths of a circuit block layout can only be accommodated within the available area when some features are disposed at minimum spacings. However, in other paths of the same layout there is available space to place features at larger spacings.
In a conventional compacting process, the spacings between features of all paths of a layout are reduced regardless of whether the features of a particular path need to be compacted to fit within the dimensional constraint of the layout. Thus, in any compacted layout, many paths may exist in which many features of those paths are at small or minimum spacings, even though the spacings could have been made larger and those paths would still fit within a predetermined dimensional constraint for the circuit block area.
Consequently, compacting may actually decrease manufacturing yields because the features of some paths of a layout are placed at unnecessarily small spacings, leading to increased problems of contamination and reduced tolerances for photolithographic patterning and etching.